The present invention relates to a semiconductor device, and in particular, to an effective technique applicable to a semiconductor device with bonding pads.
Various semiconductor integrated circuits are formed on a semiconductor wafer made of, for example, a single crystal silicon and others and then the semiconductor device wafer is separated into semiconductor chips by dicing to manufacture chip-shaped semiconductor devices. On the main surface of the semiconductor device a plurality of bonding pads acting as an external terminal are provided along the periphery of the semiconductor device.
Japanese Unexamined Patent Publication No. Hei09(1997)-283632 (Patent Document 1) sets forth a technique in which, in the semiconductor device with three or more wiring layers on which a plurality of rows of bonding pads are staggered along the periphery of a semiconductor chip, a first lead wiring electrically connecting the bonding pad in the inner row to an inner circuit is formed by one or more wiring layers including at least the wiring of the uppermost layer and a second lead wiring electrically connecting the bonding pad in the outer row to the inner circuit is formed by a plurality of wirings different from the first lead wiring.
Japanese Unexamined Patent Publication No. 2003-163267 (Patent Document 2) discloses a technique in which, in a semiconductor device provided with a cell section and a buffer circuit formed to surround the cell section, a plurality of bonding pads are formed over the periphery of the buffer circuit and over the buffer circuit and staggered over the periphery of the buffer circuit and over the buffer circuit.
(Patent Document 1) Japanese Unexamined Patent Publication No. Hei09(1997)-283632
(Patent Document 2) Japanese Unexamined Patent Publication No. 2003-163267